1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same which can maintain a threshold voltage constant despite of decreased channel width.
2. Discussion of the Related Art
A background art semiconductor device will be explained with reference to the attached drawings. FIG. 1 illustrates a section of a semiconductor device fabricated according to a background art method, FIG. 2A illustrates a graph showing a relation between a channel width vs. a doping concentration, and FIG. 2B illustrates a graph showing a relation between a channel width vs. a threshold voltage.
The semiconductor device fabricated according to a background art method is provided with a P well 4 and an N well 5 in a semiconductor substrate 1 having active regions and field regions defined thereon. And, there are trench regions formed to isolate the P well 4 and the N well 5. There is a gate oxide film 3 on surfaces of the P well 4 and N well 5 between the trenches regions 2. There are doped polysilicon layers formed on the trench isolating regions 2 and the gate oxide film 3; the polysilicon layer on the P well 4 is a first gate electrode 6 doped with N type and the polysilicon on the N well 5 is a second gate electrode 7 doped with P type. And, there is a barrier film 8 on the trench isolating region 2 which isolates the P well 4 and the N well 5, for preventing dopant inter-diffusion between the first, and second gate electrodes 6 and 7. The barrier film 8 is formed of a material, such as titanium nitride TiN. And, there is a gate cap layer 9 of a metal or a metal silicide for reducing resistances of the first, and second gate electrodes 6 and 7. A doping concentration in a channel width portion of the first gate electrode 6 of the aforementioned semiconductor device across line I--I of FIG. 1 is found constant as shown in FIG. 2A. And, as shown in FIG. 2B, a threshold voltage Vt of the semiconductor device is dropped as the channel width is decreased, which is called inverse narrow width effect. The inverse narrow width effect is caused by the following reason; a threshold voltage drop at an edge of the active region due to a low doping concentration and a threshold voltage drop at an edge of the active region due to an increased effective gate field applied on the channel when the gate electrode is placed on the edge corner of the trench isolating region 2. Such a drop of threshold voltage at the edge region implies that the threshold voltage at the edge is lower than the threshold voltage at a center portion of the active region. Accordingly, the increase of a ratio of the edge region to a total channel width when the channel width is decreased drops the device threshold voltage.
Therefore, the background art semiconductor device has the following problem.
The background art semiconductor device is involved in a drop of overall device threshold voltage as the threshold voltage of an edge region drops due to a device channel width is decreased. This variation of the device threshold voltage with the channel width makes a circuit design difficult, and the variation of the threshold voltage with the channel width in fabrication degrades a circuit operation reliability.